The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2004
Filed:
Dec. 03, 2002
Toru Endo, Kawasaki, JP;
Shoichiro Kawashima, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
An output node NO is, on one hand, connected through a PMOS transistor TP and an NMOS transistor TN to ground, and on the other hand, connected through a PMOS transistor TP and an NMOS transistor TN to a node N which is selectively set to ground and VDD. The output node NO is connected through a capacitor C to the input of a driving inverter in order to step-up or step-down the voltage of the output node NO. When the output node NO is set to −1V, the control circuit turns off the PMOS transistors TP and TP . It is also allowed to connect the output node through a first PMOS transistor to a second PMOS transistor whose back gate is connected to a power supply voltage VDD, and to connect the back gate of the first PMOS transistor to one end of a current path thereof on the side of the second PMOS transistor.