The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2004

Filed:

Jan. 25, 2002
Applicant:
Inventors:

Louis R. Nerone, Brecksville, OH (US);

David J. Kachmarik, Strongsville, OH (US);

Melvin C. Cosby, Grand River, OH (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/00 ;
U.S. Cl.
CPC ...
G05F 1/00 ;
Abstract

A ballast circuit is provided, comprising: a plurality of inverters, each inverter for powering a load; and a controller operationally coupled to a shutdown control signal of each inverter for selectively shutting down any combination of inverters. In another aspect, the controller is for selectively disabling any combination of inverters to effectively disconnect the load associated with each disabled inverter. The controller is for receiving communications from a control device, each communication a selection of 0%, “n−1” approximate percentages each associated with a ratio of “1” through “n−1” loads to “n” loads, where “n” is the total number of loads powered by the inverters of the ballast circuit and where the numerator for each ratio is an integer between “1” and “n−1,” inclusive, or 100% light from the combined loads powered by the inverters of the ballast circuit.


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