The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2004
Filed:
Oct. 31, 2002
Applicant:
Inventors:
John F. Conley, Jr., Camas, WA (US);
Yoshi Ono, Camas, WA (US);
Rajendra Solanki, Portland, OR (US);
Assignee:
Sharp Laboratories of America, Inc., Camas, WA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/100 ; H01L 2/18242 ; H01L 2/976 ; H01L 2/708 ;
U.S. Cl.
CPC ...
H01L 2/100 ; H01L 2/18242 ; H01L 2/976 ; H01L 2/708 ;
Abstract
A method of forming a layer of high-&kgr; dielectric material in an integrated circuit includes preparing a silicon substrate; depositing a first layer of metal oxide using ALD with a metal nitrate precursor; depositing another layer of metal oxide using ALD with a metal chloride precursor; and completing the integrated circuit.
Conley, Jr., John. (2004). Method to deposit a stacked high-&kgr; gate dielectric for cmos applications (U.S. Patent No. 6686212). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6686212
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile