The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2004
Filed:
Aug. 03, 2000
Javier A. Rodriguez, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A normalization circuit suitable for use in a graphics adapter is disclosed. The circuit is configured to receive vertex data and includes a set of multiplexer circuits, a set of functional units, and a control circuit. The outputs of the set of multiplexer circuits provide inputs to the set of function units and the control circuit is configured to control the select inputs of the set of multiplexer units to calculate a unit normal vector and a unit eye vector from the received vertex data. The set of functiontional units may include a pair of floating point multipliers and a floating point adder. The inputs of the first floating point multiplier may be connected to outputs of first and second mulitplexers such that the first multiplier is enabled to generate square values for x, y, and z components of the vertex data. The inputs of the floating point adder may be connected to outputs of third and fourth multiplexers, wherein the floating point adders is enabled to generate a sum of squares values. The output of the floating point adder may be coupled to the input of an inverse square circuit. A first input to the second floating point multiplier may be connected to a fifth multiplexer circuit and a second input to the second floating point multiplier may be coupled to the output of the inverse square root circuit such that the second floating point multiplier is enabled to generate x, y, and z components of the unit normal vector and the unit eye vector.