Apparatus for ensuring correct start-up and phase locking of delay locked loop

Abstract

A phase detector system and method operate correctly, regardless of the point of time at which the operation of the delay locked loop is initialized with respect to the phases of reference and feedback clock signals. The system comprises a phase detector for a delay-locked loop for compensating for a difference in phase between a first clock signal and a second clock signal. The phase detector includes a first flip-flop receiving the first clock signal and generating a first output signal, the first flip-flop being reset by a first reset signal. A second flip-flop receives the reference clock signal and generates a second output signal, the second flip-flop being reset by a second reset signal, the first and second reset signals being sourced by separate logic paths. A reset circuit generates the first reset signal based on a combination of the first and second output signals and a first initialization signal, and generates the second reset signal based on a combination of the first and second output signals and a second initialization signal.