The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2004
Filed:
Jul. 15, 2002
Robert Madge, Portland, OR (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of testing an integrated circuit. A first subset of test parameters is selected from a full set of test parameters designed to characterize given properties of the integrated circuit. A first subset of devices in the integrated circuit is tested with the first subset of test parameters, using different input levels to determine an acceptable low input level and an acceptable high input level for the first subset of test parameters on the first subset of devices. At least a second subset of devices in the integrated circuit is tested, where the second subset of devices is greater in number than the first subset of devices. The test is accomplished with at least a second subset of test parameters using the acceptable low input level and the acceptable high input level, to determine whether the integrated circuit functions properly at the acceptable low input level and the acceptable high input level. The integrated circuit is selectively binned based upon the determination of whether the integrated circuit functions properly at the acceptable low input level and the acceptable high input level.