The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2004
Filed:
Sep. 17, 2002
Applicant:
Inventor:
Platon Beletsky, Sunnyvale, CA (US);
Assignee:
Quickturn Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method for resynthesizing gated clocks in a clock cone of a logic design having more than one input clock where the logic design will be implemented in a hardware logic emulation system. By resynthesizing the gated clocks, timing in the circuit becomes predictable. In the method, predicting logic that predicts which edges of said at least two input clocks may cause a hold time violation on a gated clock is generated. Then, the outputs from the predicting logic are connected to a gated clock resolution circuit, which outputs the resynthesized clock.