The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2004
Filed:
Mar. 30, 2000
Masahiro Gion, Kyoto, JP;
Masaya Hirose, Kyoto, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
An anlog boundary scan compliant integrated circuit system carries out a test more reliably and cuts down on power dissipated during normal operation. To perform a test of whether or not an interconnect is connected normally between integrated circuits, multiple logic circuits with mutually different input threshold voltages are provided to detect the logical level of a potential at a terminal, thereby improving the reliability of the test. Potential fixers and power isolators are optionally provided. During normal operation, the power fixers fix the output potentials of the logic circuits, while the power isolators electrically isolate the logic circuits from the ground. As a result, no current flows through the logic circuits or other circuits in succeeding stages while no tests are carried out.