The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2004
Filed:
Jan. 16, 2001
Brian D. McKean, Longmont, CO (US);
Noel S. Otterness, Boulder, CO (US);
Joseph G. Skazinski, Berthoud, CO (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Structure and method for efficient failover and failback techniques in a data storage system utilizing a dual-active controller configuration for minimizing a delay in responding to I/O requests from a host system following a controller failure is described. A stripe lock data structure is defined to maintain reservation status or stripe locks of cache lines within data extents that are part of a logical unit or storage volume. When a controller fails, dirty cache line data of a failed controller is taken over by a survivor controller. The stripe lock data structure is used to process I/O requests from a host system, by the failed controller. The data storage system functions in a single-active configuration until the dirty cache line data is flushed to one or more storage volumes, by the survivor controller. The inventive structure and method provide utilize a storage volume reservation system. The stripe lock data structure is defined in memory within each of the two or more caching controllers. The stripe lock data structure is used to provide consistent information within each of the two or more caching controllers, and the stripe lock data structure is used by a failed controller to process I/O requests from a host system until dirty cache line data is flushed to one or more storage volumes by a survivor controller. Provides a method and structure which minimizes a delay required to begin processing of host I/O request following a controller failure.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile