Statistical methods and systems for data rate detection for multi-speed embedded clock serial receivers

Abstract

Methods and systems for data rate detection for multi-speed embedded clock serial receivers are described. In one embodiment, a method of determining a data rate of a high speed serially transmitted data stream comprises statistically examining edge characteristics of the incoming data stream. Based on the edge characteristics, a signature is identified that is associated with the edge characteristics. Based on the identified signature, a data rate at which the data stream is being transmitted is determined. In one embodiment, a clock extraction/data recovery circuit is provided for recovering an embedded clock and data from a high speed serially transmitted data stream. The circuit comprises a phase comparator that is configured to receive a high speed serially transmitted data stream and output indicia whenever the data stream experiences a data transition. A voltage controlled oscillator (VCO) is connected with the phase comparator and provides a clock signal having clock edges. The clock signal is locked to the data stream. A data rate detection circuit is connected with the phase comparator and receives the series of pulses that are output by the phase comparator. Based on the received pulses, the data rate detection circuit ascertains a data rate at which the data stream is transmitted.