The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2004
Filed:
Feb. 26, 2002
Applicant:
Inventors:
Steven Meyers, Round Rock, TX (US);
Nathan Y. Moyal, Austin, TX (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 ;
U.S. Cl.
CPC ...
H03L 7/06 ;
Abstract
An apparatus comprising a voltage controlled oscillator (VCO) within a phase lock loop (PLL) that may be configured to generate an output signal in response to (i) a low gain control input and (ii) a high gain control input. The low gain control input and the high gain control input are generally both active.
Meyers, Steven. (2004). Method/architecture for a low gain pll with wide frequency range (U.S. Patent No. 6680632). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6680632
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile