The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2004

Filed:

May. 02, 2002
Applicant:
Inventors:

Fumiyoshi Yoshioka, Fukuyama, JP;

Masayuki Nakano, Nara, JP;

Hiroshi Iwata, Nara-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/7108 ;
U.S. Cl.
CPC ...
H01L 2/7108 ;
Abstract

A gate oxide film ( ), a gate electrode ( ) and a gate cap insulating film ( ) are stacked on an active region of a p-type semiconductor substrate ( ), and an insulating side wall ( ) is formed, followed by BF ion implantation. Thus, a surface of the p-type semiconductor substrate becomes amorphous so that single-crystal silicon is prevented from epitaxially growing in the next process of depositing polysilicon ( ). Halo regions ( ) are formed using the BF ions having the opposite conductivity to a source/drain to reduce the short-channel effect. The substrate is then passed through a nitrogen purge chamber having a dew point kept at −100° C. to remove water molecules completely, and polysilicon ( ) is deposited. Because native oxide is prevented from growing at an interface between the active region and the polysilicon, source/drain regions ( ) formed later by implantation and diffusion of n-type impurity ions achieve a uniform junction depth.


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