The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2004
Filed:
Oct. 30, 2000
Linus Albert Fetter, Morganville, NJ (US);
Yiu-Huen Wong, Summit, NJ (US);
Michael George Zierdt, Belle Mead, NJ (US);
Agere Systems Guardian Corp., Allentown, PA (US);
Abstract
A method of producing and mounting electronic devices to negate the effects of parasitics on device performance. In one aspect, the substrate surface of the device is coated with a thin, etch-resistant film during fabrication that acts as a barrier to allow removal of substrate material beneath the film, creating a suspended structure upon which the remaining layers of circuitry rest. Alternatively the device is made with a film that is integral to the device, and that acts as the supporting membrane. To mount the device on a carrier or package, solder bumps are applied near the ends of the conductors of the device, and the die is then secured to a carrier or package, and positioned so that leads extending from the conductors mate up with bonding strips on the carrier or package. The solder bumps are then reflowed or melted to establish electrical connection between leads of the device and corresponding bonding strips of the carrier. The resultant electronic device is essentially immune to the effects or parasitic capacitanaces and parasitic inductances, with the device as mounted being further configured so as to tune out any residual parasitics which may still exist after fabrication.