The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2004
Filed:
Jun. 30, 2000
Applicant:
Inventor:
William G. Baker, Starkville, MS (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/08 ;
U.S. Cl.
CPC ...
G06F 1/08 ;
Abstract
A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. At least one of the plurality of signals may comprise an identical signal path while in the first mode and the second mode.
Quick Actions:
Baker, William. (2004). Majority vote circuit for test mode clock multiplication (U.S. Patent No. 6675312). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6675312
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile