Hierarchical connection of plurality of functional units with faster neighbor first level and slower distant second level connections

Abstract

A device for a hierarchical connection of a plurality of functional units in a processor comprises a first connector with at least two inputs and an output, which is adapted for connecting one of the inputs to the output, a second connector with at least one input and an output, which is adapted for connecting the input to the output, and a buffer connected between the output of the second connector and the input of the first connector for buffering, for at least one clock cycle, a signal applicable to the at least one input of the second connector before H is forwarded to a further input of the first connector. The output of the first connector is connected to an input of a first functional unit. An output of a second functional unit is connected to a first input of the at least two Inputs of the first connector. The at least one input of the second connector is connected to a third functional unit. A signal connection from the output of the third functional unit, which is not a neighbour to the first functional unit, and the input of the first functional unit is possible only via the second connector, the buffer and the first connector rather than via the first connector alone so that the connection between the neighbouring functional units is higher in hierarchy than the connection between non-neighbouring units.