The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2004

Filed:

Sep. 19, 1997
Applicant:
Inventors:

Nagataka Tanaka, Yokohama, JP;

Eiji Oba, Kawasaki, JP;

Keiji Mabuchi, Kitakami, JP;

Michio Sasaki, Kamakura, JP;

Ryohei Miyagawa, Sagamihara, JP;

Hirofumi Yamashita, Tokyo, JP;

Yoshinori Iida, Tokyo, JP;

Hisanori Ihara, Yokohama, JP;

Tetsuya Yamaguchi, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 3/14 ;
U.S. Cl.
CPC ...
H04N 3/14 ;
Abstract

A solid state imaging device comprises a plurality of unit cells formed in a surface region of a semiconductor substrate. Each of the unit cells comprises a photoelectric converter, an MOS-type read-out transistor for reading a signal from the photoelectric converter, an MOS-type amplifying transistor having a gate connected to a drain of the read-out transistor and for amplifying the signal read by the read-out transistor, a reset transistor having a source connected to the drain of the read-out transistor and for resetting a potential of a gate of the amplifying transistor, and an addressing element connected in series to the amplifying transistor and for selecting the unit cell. The read-out transistor is formed in a first device region in the semiconductor substrate. The reset transistor is formed in a second device region in the semiconductor substrate. The drain of the read-out transistor is connected to the source of the reset transistor through a wiring layer formed on the surface of the semiconductor substrate.


Find Patent Forward Citations

Loading…