Non-volatile semiconductor memory device and semiconductor integrated circuit

Abstract

A non-volatile semiconductor memory device includes a p-type Si substrate, an n-type well formed in the Si substrate, a control gate of a p-type buried diffusion region formed in the n-type well, an active region formed in the Si substrate in the vicinity of the n-type well and covered by a tunneling insulation film, and a floating gate electrode formed on the Si substrate so as to achieve a capacitance coupling with the p-type buried diffusion region, wherein the floating gate electrode extends on the active region over the tunneling insulation film, and the active region including a pair of n-type diffusion regions are formed at both sides of the floating gate electrode as source and drain regions, the n-type diffusion region forming the source region having an n−-type diffusion region at the side facing the n-type diffusion region forming said drain region.