The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2004

Filed:

Jun. 20, 2002
Applicant:
Inventor:

Hirokazu Sekine, Kanagawa-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/904 ; H01L 3/1306 ; H01L 3/162 ; H01L 3/300 ; H01L 3/1113 ; H01L 3/100 ;
U.S. Cl.
CPC ...
H01L 2/904 ; H01L 3/1306 ; H01L 3/162 ; H01L 3/300 ; H01L 3/1113 ; H01L 3/100 ;
Abstract

A CMOS image sensor is provided with a first pixel group and a second pixel group The first pixel group composed of a plurality of pixels arranged in a matrix at specified pitches PH and PV in the horizontal and vertical directions, respectively. The second pixel group composed of a plurality of pixels arranged similarly in a matrix shifted by about one-half of the pitches PH and PV in the horizontal and vertical directions, respectively from the matrix of the first pixel group. Each of these pixels is composed of a combination of a photodiode PD, a reset transistor RS, a driver transistor D and an address transistor AD. The reset transistors RS belonging to the first and second pixel groups and arranged in a corresponding row of the matrix are connected to a common reset line RSL. Similarly, the address transistors AD belonging to the first and second pixel groups and arranged in a corresponding row of the matrix are connected to a common address line ADL. Further, drain electrodes of two reset transistors RS contained in adjacent four pixels and drain electrodes of two address transistors are connected to a common reset drain voltage line terminal RD.


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