The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2003

Filed:

Dec. 06, 2001
Applicant:
Inventor:

Nobuyuki Ikeda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

In designing an integrated circuit, low-order blocks are arranged in a formation area of a high-order block in a core area with small spacing. Arrangement of and wiring between cells are performed in the low-order blocks. Input/output terminals used for connection between the cells also serve as signal connection terminals of the low-order blocks. Connection between the low-order blocks is performed by connecting the input/output terminals to each other with signal connection wiring. The signal connection wiring is constituted by a wiring layer and a via through a high-order block. The wiring layer and via constituting the signal connection wiring are different from the wiring layer and via used for connection between cells in low-order blocks.


Find Patent Forward Citations

Loading…