Bus system

Abstract

A bus system is provided. The bus system includes: an arbiter that receives access commands output from the plurality of master devices and outputs the access commands in an order according to a predetermined arbitration algorithm; an execution scheduler that receives the access commands from the arbiter and outputs the access commands in the order in which execution preparation by corresponding slave devices are complete; a plurality of command execution controllers corresponding to at least one of the slave devices, respectively, each command execution controller stores two or more access commands input from the execution scheduler, extracts access information necessary for execution from the stored access commands, controls the output order of the access commands based on the result of comparing the extracted access information with access information about the command currently being executed so that the total execution time of the stored commands is shorter than the total execution time according to the order in which the commands are input; and a plurality of pseudo-delayers corresponding to at least one of slave devices, respectively, each pseudo-delayer delays and outputs the access command received from the command execution controller to a corresponding slave device so that the latency period of the corresponding slave device may equal the longest of latency periods of the plurality of slave devices. Accordingly, the number of idle clock cycles of a data bus is reduced and the overall system efficiency is improved.