The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2003

Filed:

Dec. 21, 2001
Applicant:
Inventors:

Hiroko Murakami, Kasugai, JP;

Masaru Sawada, Kasugai, JP;

Manabu Nakano, Kasugai, JP;

Kazuyoshi Kikuta, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11B 5/09 ; G11B 5/00 ;
U.S. Cl.
CPC ...
G11B 5/09 ; G11B 5/00 ;
Abstract

A digital arithmetic operation circuit includes a plurality of arithmetic operation blocks, a control signal generator and a selector. The plurality of arithmetic operation blocks receive a plurality of digital input signals and perform different arithmetic operations on the received digital input signals, in parallel, to output operation result signals. The a control signal generator receives a plurality of digital input signals and generates a control signal based on the digital input signals. The selector selects one of the operation result signals, in response to the control signal, to output the selected operation result signal. After the control signal generator supplies the control signal to the selector, the selector outputs the selected operation result signal as soon as the selected operation result signal is supplied to the selector.


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