The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2003
Filed:
Nov. 05, 2002
Wangpeng Cao, San Jose, CA (US);
Chrontel, Inc., San Jose, CA (US);
Abstract
A nominal 50% duty cycle input CLKIN clock signal is processed by an adaptive circuit that outputs complementary CLK and CLKB clock signals whose duty cycle is continuously and automatically maintained at substantially 50%. The circuit includes a duty cycle adjustor circuit comprising inverter stages whose V is adjusted by a control voltage V to vary duty cycle of the CLKIN signal passing through the stages. The inverter output signal is converted to the differential CLK, CLKB signals, which are low pass filtered to obtain DC voltages that are input to a differential operational amplifier whose output is control signal V . Using the ensured substantially 50% duty cycle for CLK (or CLKB) enables data to be clocked or latch-transferred between IC stages substantially error free even if IC stage setup time varies, and clock frequency is increased. CLK duty cycle can be held to 50%±0.1% even if CLKIN duty cycle varies from 33% to 67%.