The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2003
Filed:
Jul. 19, 2002
Arnold Chow, Sunnyvale, CA (US);
Pericom Semiconductor Corp., San Jose, CA (US);
Abstract
A bus switch has a p-channel and an n-channel transistor in parallel between two buses. When power is disconnected to the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel transistor. This biasing keeps the p-channel transistor turned off. A gate connecting p-channel transistor connects the hot bus to the p-channel gate node, while a substrate connecting p-channel transistor connects the hot bus to the substrate under the p-channel transistor. A third connecting p-channel transistor connects the hot bus to a power-down node. The power-down node is normally driven low through a delay line when power is applied. The power-down node is applied to the gate of a source transistor that connects power to the substrate and to an inverter that normally drives the p-channel gate node.