The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2003

Filed:

Jan. 23, 2002
Applicant:
Inventor:

Shoichi Kawamura, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ;
U.S. Cl.
CPC ...
H01L 2/976 ;
Abstract

The invention is to provide a novel non-volatile memory capable of recording multi-bit data. The invention is a non-volatile memory which has: first and second source-drain regions SD , SD at the surface of a semiconductor substrate; and a non-conductive trapping gate TG, and a conductive control gate CG, formed on a channel region there between via an insulating film. Further, the non-volatile memory has a first or second state in which, by applying a voltage between the first and second source-drain regions SD , SD , hot electrons produced in the vicinity of the first or second source-drain region are locally captured in a first or second trapping gate region TSD , TSD in the vicinity of them; and, a third state in which, by applying a voltage between the control gate and the channel region, electrons (or charge) are (is) injected into the entire trapping gate. According to whether or not the above-mentioned third state is adopted, one-bit information can be recorded, and according to whether or not the first and second states are adopted, two-bit information can be recorded. Consequently, information totaling three bits can be recorded in a single memory cell.


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