The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2003
Filed:
Jan. 07, 2002
Thomas Peter Haneder, Dachau, DE;
Harald Bachhofer, München, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between source/drain regions at the surface of a semiconductor substrate. The first gate intermediate layer contains at least one ferroelectric layer. Beside the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are disposed between the source/drain regions, the second gate intermediate layer containing a dielectric layer. The first gate electrode and the second gate electrode are connected to one another through a diode structure. Strip-type doped well regions are provided in the semiconductor substrate, which well regions run between the source/drain regions of the respective ferroelectric transistor.