The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2003

Filed:

Jul. 18, 2000
Applicant:
Inventor:

Hideyuki Nakamura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/128 ; G11C 7/00 ;
U.S. Cl.
CPC ...
G01R 3/128 ; G11C 7/00 ;
Abstract

To provide such a memory-mounting integrated circuit as well as a memory test method that can reduce costs to incur for a tester, regulate the number of the input-output terminals for testing, and nevertheless can monitor from outside all the contents of defects in principle. The memory-mounting integrated circuit on which at least a BIST circuit and a memory are mounted, in which the above described BIST circuit includes a data storing apparatus to store the data in a normal memory, a comparing apparatus to compare a memory test result signal from the above described memory with data from the above described data storing apparatus to output a first comparing signal, a control apparatus to control to implement outputting outward from the first comparing signal outputted by the above described comparing apparatus, and an output apparatus to output defective data outward by the above described control apparatus.


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Nakamura, Hideyuki. (2003). Memory-mounting integrated circuit and test method thereof (U.S. Patent No. 6668348). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6668348

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