The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2003

Filed:

Mar. 25, 2003
Applicant:
Inventors:

Shigeo Chaya, Shiga, JP;

Masanori Matsuura, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/134 ;
U.S. Cl.
CPC ...
G11C 1/134 ;
Abstract

The semiconductor memory of this invention includes a memory cell, a control word line selector/deriver circuit, a well driver circuit, a source line selector/deriver circuit, a pulse generation circuit for outputting a pulse signal in injecting electrons into a floating gate of the memory cell, a first delay circuit, a second delay circuit and a third delay circuit. The control word line selector/deriver circuit changes the potential of a control word line in response to a first delay signal received from the first delay circuit, the well driver circuit changes the potential of a well in response to a second delay signal received from the second delay circuit, and the source line selector/deriver circuit changes the potential of a source line in response to a third delay signal received from the third delay circuit.


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