Nand type core cell structure for a high density flash memory device having a unique select gate transistor configuration

Abstract

A method of forming a NAND-type flash memory device including forming a stacked gate flash memory structure ( ) containing an interpoly dielectric layer ( ) for one or more flash memory cells in a core region ( ). The method also includes forming a select gate transistor structure ( ) having a first gate oxide ( ) formed of the interpoly dielectric material and a gate conductor ( ) overlying the first gate oxide ( ) in the core region ( ). A NAND-type flash memory device includes a core region ( ) comprising a stacked gate flash memory cell structure ( ) and a select gate transistor ( ) and a periphery region ( ) comprising a low voltage transistor ( ) and a high voltage transistor ( ). The stacked gate flash memory cell structure ( ) includes a tunnel oxide layer ( ), a poly layer ( ) overlying the tunnel oxide layer ( ), an interpoly dielectric layer ( ) formed of an insulating material overlying the poly layer ( ) and a poly layer ( ) overlying the interpoly dielectric layer ( ). In addition, the select gate transistor structure ( ) includes a gate insulator ( ) formed of the insulating material and a poly layer ( ) overlying the gate insulator ( ).