The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2003
Filed:
Mar. 19, 2002
Applicant:
Inventors:
Michael A McCurdy, Fort Collins, CO (US);
Edward Chang, Fort Collins, CO (US);
Assignee:
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/9094 ;
U.S. Cl.
CPC ...
H03K 1/9094 ;
Abstract
A pseudo-NMOS circuit includes a load PFET electrically connected between a power supply and an output node, and an NFET circuit having a plurality of inputs connected between the output node and ground. A feedback PFET is electrically connected between the power supply and the output node, in parallel with the load PFET, and is controlled by a signal at the output node of the pseudo-NMOS circuit.
McCurdy, Michael. (2003). Pseudo-nmos logic having a feedback controller (U.S. Patent No. 6664813). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6664813
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile