Digital delay line-based phase detector

Abstract

A digital delay line-based, timing relationship detector is operative to generate a K+L bit digital output code representative of a timing/phase offset between first and second low frequency clock signals. A first digital code generator generates a K-bit most significant phase word based upon the number of high frequency clock signals counted between transitions in the two low frequency clock signals. A second digital code generator generates an L-bit least significant phase word based upon the effective length of a delay line/shift register, through which a digital value associated with a transition in one of the two clock signals propagates, until a transition of the next occurring high frequency clock signal. The contents of a counter are incrementally changed in accordance with the number of stages of the multistage digital delay line/shift register through which the digital value has propagated. The L-bit least significant phase word is defined in accordance with the contents of the counter.