Semiconductor memory, semiconductor integrated circuit and semiconductor mounted device

Abstract

A semiconductor memory comprising: a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction; a memory cell array constituted by the sub-memory cell arrays arranged in the first and a second direction; a plurality of local bit lines in the sub-memory arrays; a plurality of word lines in the sub-memory arrays; a plurality of global bit lines connected the local bit lines via switching circuits; a plurality of read/write circuits connected to the global bit lines; a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus; a sub-memory cell array selecting circuit connected to the switching circuits, decoding the first and second address signals, and selecting a first sub-memory cell array, and a second sub-memory cell array; and an address decoding circuit decoding the first and second address signals, and activating a first word line connected to a memory cell of the first sub-memory cell array and a second word line connected to another memory cell of the second sub-memory cell array.