The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2003
Filed:
May. 25, 2001
Sasan Cyrusian, Scotts Valley, CA (US);
Stephen J. Franck, Felton, CA (US);
Sriharsha Annadore, Santa Cruz, CA (US);
Elmar Bach, Santa Cruz, CA (US);
Siegfried Hart, Santa Cruz, CA (US);
Thomas Blon, Santa Cruz, CA (US);
William G. Bliss, Thornton, CO (US);
James Wilson Rae, Rochester, MN (US);
Michael Ruegg, Santa Cruz, CA (US);
Ulrich Huewels, Santa Cruz, CA (US);
Fritz Mistlberger, Sudmahrerweg 1, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A method and apparatus for running an analog portion ( ) of a read/write channel ( ) from a highly regulated power supply ( ). The apparatus includes an analog portion ( ), a clock synthesizer ( ), and a highly regulated power supply ( ) connected to the analog portion ( ) and the clock synthesizer ( ). The analog portion ( ) and the clock synthesizer ( ) both comprise high voltage transistors which operate in a first voltage range and low voltage transistors which operate in a second voltage range, wherein the first voltage range is within the second voltage range. The highly regulated power supply ( ) supplies power that is within the first voltage range to the analog portion ( ) and the clock synthesizer ( ). The method includes generating power that is within the first voltage range using the highly regulated power supply ( ), and supplying the power to the analog portion ( ) and the clock synthesizer ( ).