The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2003
Filed:
Dec. 07, 2001
Jeffrey Dunnihoo, Austin, TX (US);
Cirrus Logic, Inc., Austin, TX (US);
Abstract
A method of controlling a power supply having an output activated in response to a first logic level of a control signal and deactivated in response to a second logic level of the control signal. A clock is generated on a second power source and used to time a time-out period of a selected number of clock periods. In response to the step of sensing, if the state of the output of the power supply is inactive through the timeout period, then the first logic level of the control signal is generated to activate the power supply for use in powering operations of an associated device. After completion of these operations, the second logic level of the control signal is generated to deactivate the power supply. If however, the state of the output of the power supply is active during the time-out period, then the first logic level of the control signal is maintained to power operations of the associated device. At the end of these operations, the second logic level of the control signal is generated to deactivate the power supply.