The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2003
Filed:
Jul. 02, 2002
Jie Zhang, Buffalo Grove, IL (US);
Paul Brazis, South Elgin, IL (US);
Daniel Gamota, Palatine, IL (US);
Krishna Kalyanasundaram, Chicago, IL (US);
Steven Scheifers, Hoffman Estates, IL (US);
Jerzy Wielgus, Park Ridge, IL (US);
Abhijit Roy Chowdhuri, Oak Park, IL (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
An integrated circuit ( ) that includes a field effect transistor ( ) is fabricated by forming an organic semiconductor channel ( ) on one substrate ( ), forming device electrodes ( ) on one or more other substrates ( ), and subsequently laminating the substrates together. In one embodiment, a dielectric patch ( ) that functions as a gate dielectric is formed on one of the substrates ( ) prior to performing the lamination. Lamination provides a low cost route to device assembly, allows for separate fabrication of different device structures on different substrates, and thins various device layers resulting in improved performance.