The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2003

Filed:

Oct. 28, 2002
Applicant:
Inventor:

Wolfgang Welser, Kirchheim, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ;
U.S. Cl.
CPC ...
H01L 2/1302 ;
Abstract

In a fabrication method for making spatially etched structures, in particular trench structures for semiconductor memory cells, in a semiconductor substrate made of a semiconductor material, a depth structure is produced in a surface of the semiconductor substrate. Afterward, an etching-resistant layer is deposited in a region of a sidewall of the depth structure, so that the sidewall is essentially not etched during subsequent etching steps. Afterward, an etchant is introduced into the depth structure and a potential field is applied in the semiconductor substrate. As a result, a spatial structure is etched proceeding from a region of the depth structure that is not covered by the etching-resistant layer, the spatial structure being dependent on the potential field.


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