The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2003
Filed:
Dec. 19, 2001
Developement of hardmac technology files (clf, tech and synlib) for rtl and full gate level netlists
Applicant:
Inventors:
Robert E. Landy, San Jose, CA (US);
Michael Porter, Milpitas, CA (US);
Peter F. Lindberg, Maple Grove, MN (US);
Craig R. Lang, Brooklyn Center, MN (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
A method for generating one or more hardmacro technology files comprising the steps of determining a netlist, generating a timing constraints file in response to (i) the netlist and (ii) a time budget, and generating the hardmacro technology files in response to (i) the netlist and (ii) the timing constraints file.
Landy, Robert. (2003). Developement of hardmac technology files (clf, tech and synlib) for rtl and full gate level netlists (U.S. Patent No. 6658628). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6658628
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile