The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2003
Filed:
Dec. 07, 1999
Boe-Hydis Technology Co., Ltd., Kyoungki-do, KR;
Abstract
Liquid crystal display having fast response time and preventing color shift is disclosed. The liquid crystal display comprises: a lower substrate having a plurality of gate bus lines disposed parallel to each other, a plurality of data bus lines disposed perpendicular to the gate bus lines and defining matrix type sub pixels together with the gate bus lines, a thin film transistor provided adjacent to an intersection of the gate bus line and the data bus line, and a pixel electrode connected to the thin film transistor and disposed within the sub pixel; an upper substrate opposed to the lower substrate with a selected distance and having a counter electrode, the counter electrode formed at a portion corresponding to the sub pixel and forming an electric field together with the pixel electrode; a liquid crystal layer sandwiched between and having a plurality of liquid crystal molecules; a first homeotropic alignment layer and a second homeotropic alignment layer formed at inner face of the lower substrate and at inner face of the upper substrate respectively; and a first polarizing plate and a second polarizing plate attached at outer face of the lower substrate and at outer face of the upper substrate respectively, wherein the electric field formed between the counter electrode and the pixel electrode is formed as an oblique line with respect to the lower substrate surface, and is formed as a diagonal line having a symmetry with respect to the data bus line and the gate bus line.