The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2003
Filed:
Apr. 10, 1998
Mark W. Rouse, Santa Clara, CA (US);
Andrew Walker, Mountain View, CA (US);
Brenor Brophy, San Jose, CA (US);
Kenelm Murray, Sunnyvale, CA (US);
Cypress Semiconductor Corp., San Jose, CA (US);
Abstract
A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (V ) and/or V for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n -type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.