The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2003

Filed:

Apr. 13, 2001
Applicant:
Inventors:

Renganathan Ashokan, Darien, IL (US);

Paul Boieriu, Chicago, IL (US);

Yuanping Chen, Rockville, MD (US);

Jean-Pierre Faurie, Chicago, IL (US);

Sivalingam Sivananthan, Naperville, IL (US);

Assignee:

EPIR Technologies, Inc., Bolingbrook, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 3/109 ;
U.S. Cl.
CPC ...
H01L 3/109 ;
Abstract

At a face of a silicon semiconductor substrate tilted about one degree from a [100] orientation, a readout integrated circuit (ROIC) is implemented, specially designed and fabricated for direct epitaxial growth. Layers of II-VI semiconductor material, preferably including layers of HgCdTe of different bandgaps, are successively and monolithically grown on the face by molecular beam epitaxy (MBE) within a window masking the face and then patterned and wet-etched to create mesas of two-color detector elements in an array. Preferably a beginning buffer layer of CdTe is grown to minimize crystalline mismatch between the Si and the HgCdTe. Sloped sidewalls of the mesas ensure good step coverage of the conductive interconnects from the detector elements to the ROIC.


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