Fabricating ferroelectric memory device with photoresist and capping layer

Abstract

Methods for fabricating a ferroelectric memory device are disclosed, in which the cracking of the ferroelectric thin film can be inhibited during a heat treatment in a scribe lane region (for forming an aligning key and an overlay vernier). A first interlayer dielectric film is formed upon a semiconductor substrate on which the transistor has been formed. The first interlayer dielectric film is selectively etched to form a first contact hole and to expose a source/drain. A first conductive film is formed on an entire surface that includes the first contact hole. The first conductive film is selectively etched to form a first conductive pad, the first conductive pad being connected through the first contact hole to the source/drain. A second interlayer dielectric film is formed on an entire surface that includes the first conductive film. The second interlayer dielectric film is selectively etched to form a second contact hole and to expose the first conductive pad so as to form an aligning key region in the scribe lane region. A second conductive film is formed on an entire surface that includes the second contact hole. The second conductive film is selectively etched to form a plug, the plug being connected through the second contact hole to the first conductive pad.