The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2003
Filed:
Jun. 20, 2000
Ashutosh Misra, Bangalore, IN;
Seetharam Gundu Rao, Bangalore, IN;
Anil Shrikant Keste, Bangalore, IN;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A dual master apparatus for mastering a Processor Local Bus (PLB), which is a high-performance, on-chip bus used in many System on Chip (SOC) applications, supporting up to 16 masters. The apparatus includes a first circuit for generating an address phase for read data coupled to the PLB, and a second circuit for generating an address phase for write data coupled to the PLB. The second address phase generating circuit is adapted to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa. The first and second address phase generating circuits can simultaneously process read and write requests. The apparatus also may include circuits for handling read and write data coupled to the first and second address generating circuits, respectively. Further, the apparatus may include circuits for requesting read and write data coupled to the read- and write-data handling circuits, respectively.