The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2003
Filed:
Feb. 18, 2000
Gerard M Blair, Fort Collins, CO (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
What is described is a method to reduce variations in signal delays along paths in a design of an integrated circuit by balancing wire widths. The method operates by performing a circuit simulation to determine simulated signal delays along the circuit paths based on first wire widths for a given circuit, then running a delay model analysis to calculate predicted signal delays along the circuit paths based on first wire widths for the given circuit. The method then calculates a correction difference between the predicted signal delays and the simulated signal delays, and derives delay targets from the correction difference. Finally, the method calculates second wire widths using the delay model analysis to meet the delay targets. Preferably, the signal delays are clock signal delays, the circuit simulation is a SPICE circuit simulation, and the delay model is an Elmore delay model. Also described is a system which includes a CPU and certain memory components for accomplishing the method. Further described is a computer readable medium on which is embedded a program containing the components that execute the described method.