The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2003

Filed:

Feb. 26, 2001
Applicant:
Inventor:

Kaneyasu Shimoda, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/30 ;
U.S. Cl.
CPC ...
H03H 7/30 ;
Abstract

“100”, which is one of the (1, 7) RLL codes, is used as a clock acquisition pattern. After temporarily judging the sample output to be one of (1, −1), the phase error computing result for three samples (symbols) is added so as to cancel the errors of phase computing. Therefore the number of judgment states can be decreased, and phase can be acquired at high-speed even if the amplitude at acquisition has not been defined. At tracking, the sample output is judged to be one of three groups, [1+a, 1], 0, and [−1, −1−a]. Using the state transition of (1, 7) RLL codes, [1+a, 1] and [−1, −1−a] are distinguished. Since the number of judgment states decreases, judgment accuracy improves.


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