The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2003

Filed:

Jul. 10, 2002
Applicant:
Inventors:

Hideki Osaka, Oiso, JP;

Toyohiko Komatsu, Yokohama, JP;

Takashi Tsunehiro, Ebina, JP;

Koichi Kimura, Kamakura, JP;

Susumu Hatano, Higashimurayama, JP;

Kazuya Ito, Hamura, JP;

Toshio Sugano, Kodaira, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 ; G11C 5/06 ;
U.S. Cl.
CPC ...
G11C 5/02 ; G11C 5/06 ;
Abstract

Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.


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