Clock producing circuit capable of suppressing phase shift at a time of change from active clock to standby clock

Abstract

A clock producing circuit comprises a phase comparator to produce a comparison signal representing phase difference between a first output clock produced by a first PLL and a second output clock produced by a second PLL. The comparison signal is supplied to a digital filter included in the second PLL. The digital filter updates filter coefficients thereof to reduce the phase difference while the first output clock is selected as a selected output signal. Thus, the second output clock coincides the first output clock in phase. If the first reference clock disappears, the second output clock instead of the first output clock is selected as the selected output clock. At the same time, the digital filter stops updating the filter coefficients. A phase shift is not caused in the selected output clock by changing from the first output clock to the second output clock.