The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2003

Filed:

Dec. 22, 2000
Applicant:
Inventors:

Richard Fournel, Lumbin, FR;

Eric Mazaleyrat, Crolles, FR;

Assignee:

STMicroelectronics S.A., Gentilly, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/9788 ;
U.S. Cl.
CPC ...
H01L 2/9788 ;
Abstract

An integrated circuit including logic MOS transistors, EPROM cells, and high-voltage MOS transistors. Each EPROM cell includes a floating gate formed from a first polysilicon level above a tunnel oxide and a control gate formed from a second polysilicon level. Each logic MOS transistor includes a gate formed from a portion of the second polysilicon level above a very thin oxide. Each high-voltage transistor includes a gate corresponding to a portion of the first polysilicon level above a layer of said tunnel oxide, the gate being covered with a portion of the second polysilicon layer, except at locations where a contact is desired to be made with the gate. The uncovered portion of the first polysilicon layer in the high-voltage MOS transistors is coated with a silicon nitride layer.


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