Cmos integrated circuit having vertical transistors and a process for fabricating same

Abstract

A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.