Method of optimizing signal lines within circuit, optimizing apparatus, recording medium having stored therein optimizing program, and method of designing circuit and recording medium having stored therein program for designing circuit

Abstract

There is provided a method utilized when designing an integrated circuit such as a VLSI or the like. The method is utilized for optimizing the delay of a signal transmitting through signal lines connecting a signal supplying source to each of elements, whereby skew can be positively decreased. The method includes a step (S ) of determining whether or not the signal supplying source satisfies a fan-out restriction if the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source, a step (S ) of dividing the plurality of elements into a plural number of groups so that the fan-out restriction is satisfied in each of the groups and that each of the groups has the same or substantially the same load capacity, when it is determined that the signal supplying source does not satisfy the fan-out restriction, and a step (S ) of inserting into each of the groups, a buffer element having a size which makes the groups of elements satisfy the fan-out restriction. The buffer element inserted at the buffer inserting step (S ) is regarded as a driven element and then it is again determined in the determining step (S ) whether or not the signal supplying source satisfies the fan-out restriction under the condition that the signal supplying source supplies a signal to all of the driven elements which are directly connected to the signal supplying source. The dividing step (S ) and the buffer inserting step (S ) are repeatedly carried out until positive determination is delivered on the fan-out restriction.