The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2003
Filed:
May. 20, 1999
Paul T. Wildes, Eau Claire, WI (US);
Edward J. O'Neill, Cadott, WI (US);
Silicon Graphics, Inc., Mountain View, CA (US);
Abstract
A method for determining optimum locations for scan latches using traditional fault-simulation and some additional 'bookkeeping.' A logic simulation is run on the IC, with single stuck-at faults injected into the circuit. The entire test set is run and records are kept of which faults are detected at every latch in the system. After the simulation run, the statistics gathered are used to indicate which system latches are the best candidates for conversion to scan latches: A high count of faults indicates high observability at that point. This can be further refined by looking at total faults covered by given sets of latches. This permits maximizing fault coverage while minimizing resources. In addition, the software can keep a transition count at each latch's output, to enable the already established method of using transition counts to measure testability. A low transition count indicates a desirable place for a scan latch.