High-speed memory controller for pipelining memory read transactions

Abstract

A memory controller ( ) is disclosed which includes a write arbiter ( ) and a read arbiter ( ) for receiving and processing memory requests from a number of requestor modules ( ) for accessing a high speed memory device ( ). A high speed controller ( ) controls data flow to and from the high speed memory device ( ) at a frequency that is higher than ail operating of the arbiters ( ), allowing pseudo-simultaneous memory transactions. A read data dispatcher ( ) is also disclosed for receiving data from the high speed controller ( ) in response to read transactions and for passing the data to one of the requestor modules ( ). The size and destination information for launched read transactions are kept by a queue . When return data is received by the read data dispatcher ( ), the read data dispatcher ( ) matches the appropriate amount of data with each queue entry and delivers that return data to the appropriate requester module ( ).